This relates to a circular first in, first out (FIFO) buffer and in particular to one useful in data communication applications to accommodate different clocking rates.
A FIFO buffer of the prior art consists essentially of a serial input, serial output shift register. Input data is supplied to an input of the shift register, data is shifted through the register by a clock signal, and output data is derived from an output of the register. Such a system however is relatively slow and/or power intensive because data must be physically moved through a series of flip flops in the register. Moreover, to produce an output signal, it is necessary to move the data through every cell of the shift register.